1. Field of the Invention
The preset invention relates to a reset circuit for initializing a semiconductor integrated circuit, and more particularly to a reset circuit for initializing a plurality of modules arranged in a large-scale integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit has recently been integrated on a large scale (LSI) and constituted to include a plurality of modules which carry out parallel operations. Such a large-scale integrated circuit (LSI circuit, referred to as LSI hereinafter) comprises a reset input terminal which inputs a reset signal to initialize the plurality of modules. The reset signal supplied from the outside of the LSI to the reset input terminal is input to a register arranged in each module in the LSI. The register detects rising or falling of the reset signal to be reset, thereby setting an initial value. For example, when a reset signal that is changed from “1” (High level) to “0” (Low level) is supplied immediately after power is turned on, the plurality of modules in the LSI are initialized. Then, when the reset signal becomes “1”, the resetting of the module is released to set a normal state.
Additionally, in the case of an LSI configuration in which each module functions in synchronization with a clock signal supplied thereto, upon reception of the reset signal from the outside of the LSI, each module is initialized in synchronization with rising or falling of the clock signal.
In this case, for example, an arithmetic element for calculating a logical product of a data input and a reset input, and a memory element (register) for storing various values are arranged in each module. An output of the arithmetic element is input to the register. The register fetches the logical product of the reset signal and the data input to output it in synchronization with the rising of the clock signal. Accordingly, when “0” is input as the reset input, “0” is fetched into the register to complete the initialization in synchronization with the rising of the clock signal.
When the reset input is “1”, each module outputs indetermination. When the reset input becomes “0”, each module is initialized in synchronization with the rising of the clock signal. Subsequently, when the reset signal becomes “1”, the resetting of the module is released to set a normal state in synchronization with the rising of the clock signal.
However, in the case of the aforementioned LSI which comprises the plurality of modules, there is a problem that the registers arranged in all the modules in the LSI are initialized at timing when the reset signal becomes “0”, and this initializing operation is accompanied by temporary flowing of a large current to the LSI. Additionally, the current continues to flow for a period in which the reset signal is held in the register until the reset signal is changed from “0” to “1” to release the resetting. Consequently, when power is consumed and, for example, in the case of an LSI incorporated in a device such as a wireless remote controller driven by a battery, there is a problem that a battery life is greatly affected.
Furthermore, in the conventional synchronous reset circuit, there is a problem that since all the registers in the LSI are simultaneously initialized in synchronization with the clock signal, a large current instantaneously flows to increase a maximum current consumption value, consequently affecting operations of peripheral circuits. In this case, the life of the battery used in the battery-driven device is affected similarly to the above.